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uc1856-sp slusbv6 ? april 2014 uc1856-sp improved current-mode pwm controller 1 features 3 description the uc1856 is a high-performance version of the 1 ? pin-for-pin compatible with the uc1846 popular uc1846 series of current-mode controllers, ? 65-ns typical delay from shutdown to outputs, and is intended for both design upgrades and new and 50-ns typical delay from sync to outputs applications where speed and accuracy are ? improved current-sense amplifier with reduced important. all input-to-output delays have been minimized, and the current sense output is slew-rate noise sensitivity limited to reduce noise sensitivity. fast 1.5-a peak ? differential current sense with 3-v common- output stages have been added to allow rapid mode range switching of power fets. ? trimmed-oscillator discharge current for a low-impedance ttl-compatible sync output has accurate deadband control been implemented with a tri-state function when ? accurate 1-v shutdown threshold used as a sync input. ? high-current dual totem-pole outputs (1.5-a internal-chip grounding has been improved to peak) minimize internal noise caused when driving large ? ttl compatible oscillator sync pin thresholds capacitive loads. this improvement, in conjunction ? 4-kv esd protection with the improved differential current-sense amplifier, results in enhanced noise immunity. 2 applications other features include a trimmed oscillator current (8%) for accurate frequency and dead-time control; a ? dc-dc converters 1-v 5% shutdown threshold; and 4-kv minimum ? supports various topologies: electrostatic discharge (esd) protection on all pins. ? push-pull, forward, half-bridge, full bridge ? available in military temperature range (-55 c to device information (1) 125 c) device name package body size cdip (16) 20.57 mm x 7.37 mm uc1856-sp cfp (16) 10.16 mm x 7.1 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. block diagram 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. productfolder sample &buy technical documents tools & software support &community
uc1856-sp slusbv6 ? april 2014 www.ti.com table of contents 8.2 functional block diagram ......................................... 8 1 features .................................................................. 1 8.3 feature description ................................................... 8 2 applications ........................................................... 1 8.4 device functional modes ....................................... 12 3 description ............................................................. 1 9 applications and implementation ...................... 13 4 revision history ..................................................... 2 9.1 application information ............................................ 13 5 pin configuration and functions ......................... 3 9.2 typical applications ................................................ 13 6 specifications ......................................................... 4 10 power supply recommendations ..................... 17 6.1 absolute maximum ratings ...................................... 4 11 layout ................................................................... 17 6.2 handling ratings ....................................................... 4 11.1 layout guidelines ................................................. 17 6.3 recommended operating conditions ....................... 4 12 device and documentation support ................. 19 6.4 thermal information .................................................. 4 12.1 trademarks ........................................................... 19 6.5 electrical characteristics ........................................... 5 12.2 electrostatic discharge caution ............................ 19 7 parameter measurement information .................. 7 12.3 glossary ................................................................ 19 8 detailed description .............................................. 8 13 mechanical, packaging, and orderable 8.1 overview ................................................................... 8 information ........................................................... 19 4 revision history date revision notes april 2014 * initial release 2 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: uc1856-sp
uc1856-sp www.ti.com slusbv6 ? april 2014 5 pin configuration and functions 16-pin j and hkt packages (top view) pin functions pin i/o description name no. cl ss 1 i current limit/soft start vref 2 o 5.1v internally generated reference cs- 3 i inverting input of current sense operational amplifier cs+ 4 i non-inverting input of current sense operational amplifier ea+ 5 i non-inverting input of error amplifier ea- 6 i inverting input of error amplifier comp 7 o output of error amplifier timing capacitance. capacitor connected from ct to ground is charged via current ct 8 i established by rt pin via current mirror. output pulse dead time is determined by the size of the capacitor during capacitor discharge time. determines oscillator frequency. vref sources thru rt to create a current which is mirrored rt 9 i to ct pin. sync pin is an output under normal operation when rt is above 4.1v sync output high. sync sync 10 i/o pin is an input when rt pin is high and ct pin tied low. aout 11 o output driver (source/sink) gnd 12 - ground connection vc 13 i gate drive collector supply voltage. decouple with capacitor. bout 14 o output driver (source/sink) vin 15 i input voltage decouple with capacitor shutdown 16 i shutdown threshold 1v. voltage above threshold latches off oscillator. copyright ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: uc1856-sp
uc1856-sp slusbv6 ? april 2014 www.ti.com 6 specifications 6.1 absolute maximum ratings (1) (2) min max unit supply voltage 40 v collector supply voltage 40 v current sense inputs ? 0.3 3 v error amplifier inputs ? 0.3 v in v shutdown input ? 0.3 10 v error-amplifier output current ? 5 ma dc 0.5 output current, a source or sink pulse (0.5 s) 2 oscillator charging current 5 ma soft-start sink current 50 ma sync output current 10 ma junction temperature ? 55 150 c lead temperature (soldering, 10 sec.) 300 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to ground. currents are positive into, negative out of the specified pin. consult packaging section of databook for thermal/imitations and considerations of package. 6.2 handling ratings min max unit t stg storage temperature range -65 150 c 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit t j operating junction temperature -55 125 c 6.4 thermal information (1) uc1856-sp thermal metric (2) unit 16 pin r jc(bottom) j package 7.3 c/w hkt package 2.9 (1) hkt: computational fluid dynamics (cfd) model of 16 pin hkt package to mil std 883 method 1012.1 standard. 16/j: curve based on cfd models correlated to available physical measurement data points. reference: http://www.sh.sc.ti.com/process- packaging/pkgchar/tjc_by_die_size.htm (2) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 4 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: uc1856-sp
uc1856-sp www.ti.com slusbv6 ? april 2014 6.5 electrical characteristics unless otherwise stated, these specifications apply for t a ? 55 c to +125 c, v in = 15 v, r t = 10 k , c t = 1 nf, t a = t j . parameter test conditions min typ max unit reference section output voltage t j = 25 c, l o = 1 ma 5.05 5.1 5.15 v line regulation v in = 8 to 40 v 20 mv load regulation l o = ? 1 ma to ? 10 ma 15 mv total output variation line, load, and temperature 5 5.2 v output noise voltage 10 hz < f < 10 khz, t j = 25 c 50 v long-term stability t j = 125 c, 1000 hrs (1) 5 25 mv short-circuit current v ref = 0 v ? 25 ? 45 ? 65 ma oscillator section t j = 25 c 180 200 220 initial accuracy khz over operating range 170 230 voltage stability v in = 8 to 40 v 2% t j = 25 c, v ct = 2 v 7.5 8 8.8 discharge current ma over operating range, v ct = 2 v 6.7 8 8.8 sync output high level l o = ? 1 ma 2.4 3.6 v sync output low level l o = 1 ma 0.2 0.4 v sync input high level c t = 0 v, r t = v ref 2 1.5 v sync input low level c t = 0 v, r t = v ref 1.5 0.8 v sync input current c t = 0 v, r t = v ref , v sync = 5 v 1 10 a sync delay to outputs c t = 0 v, r t = v ref , v sync = 0.8 to 2 v 50 100 ns error amplifier section input offset voltage v cm = 2 v 5 mv input bias current ? 1 a input offset current 500 na common mode range v in = 8 v to 40 v 0 v in -2 v open loop gain v o = 1.2 v to 3 v 80 100 db unity gain bandwidth t j = 25 c 1 1.5 mhz cmrr v cm = 0 v to 38 v, v in = 40 v 75 100 db psrr v in = 8 v to 40 v 80 100 db output sink current v id = ? 15 mv, v comp = 1.2 v 5 10 ma output source current v id = 15 mv, v comp = 2.5 v ? 0.4 ? 0.5 ma output high level v id = 50 mv, r l (comp) = 15 k 4.3 4.6 4.9 v output low level v id = ? 50 mv, r l (comp) = 15 k 0.7 1 v current sense amplifier section amplifier gain v cs ? = 0 v, cl ss open (2) (3) 2.5 2.75 3 v/v maximum differential-input signal cl ss open (2) , r l (comp) = 15 k 1.1 1.2 v (v cs + ? v cs ? ) input offset voltage v cl ss = 0.5 v, comp open (3) 5 35 mv cmrr v cm = 0 v to 3 v 60 db psrr v in = 8 v to 40 v 60 db input bias current v cl ss = 0.5 v, comp open (2) ? 1 1 a input offset current v cl ss = 0.5 v, comp open (2) ? 1 1 a input common-mode range 0 3 v v ea + = vref, ea ? = 0 v delay to outputs 120 250 ns cs+ ? cs ? = 0 v to 1.5 v (1) this parameter, although ensured over the recommended operating conditions, is not 100% tested in production. (2) parameter measured at trip point of latch with v ea + = vref, v ea ? = 0 v. (3) amplifier gain defined as: copyright ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: uc1856-sp comp cs cs v g ; v 0 to 1 v v d = d - = d +
uc1856-sp slusbv6 ? april 2014 www.ti.com electrical characteristics (continued) unless otherwise stated, these specifications apply for t a ? 55 c to +125 c, v in = 15 v, r t = 10 k , c t = 1 nf, t a = t j . parameter test conditions min typ max unit current limit adjust section current limit offset v cs ? = 0 v , v cs + = 0v, comp = open (4) 0.43 0.5 0.57 v input bias current ? 10 ? 30 a shutdown pin section threshold voltage 0.95 1 1.05 v input voltage range 0 5 v minimum latching current (i cl ss ) see (5) 3 1.5 ma maximum non-latching current (i cl ss ) see (6) 1.5 0.8 ma delay to outputs v shutdown = 0 v to 1 .3 v 65 110 ns output section collector-emitter voltage 40 v off-state bias current vc = 40 v 250 a l out = 20 ma 0.1 0.5 output low level v l out = 200 ma 0.5 2.6 l out = ? 20 ma 12.5 13.2 output high level v l out = ? 200 ma 12 13.1 rise time c1 = 1 nf 40 80 ns fall time c1 = 1 nf 40 80 ns uvlo low saturation v in = 0 v, l out = 20 ma 0.8 1.5 v pwm section maximum duty cycle 45% 47% 50% minimum duty cycle 0% undervoltage lockout section startup threshold 7.7 8 v threshold hysterisis 0.7 v total standby current supply current 18 23 ma (4) parameter measured at trip point of latch with v ea + = vref, v ea ? = 0 v. (5) current into cl ss ensued to latch circuit into shutdown state. (6) current into cl ss ensured not to latch circuit into shutdown state. 6 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: uc1856-sp
uc1856-sp www.ti.com slusbv6 ? april 2014 7 parameter measurement information bypass caps should be low esr and esl type. short e/a ? and comp for unity gain testing. the use of a ground plane is highly recommended. figure 1. uc1856 open-loop test circuit copyright ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: uc1856-sp
uc1856-sp slusbv6 ? april 2014 www.ti.com 8 detailed description 8.1 overview the uc1856 is a high-performance version of the popular uc1846 series of current-mode controllers, and is intended for both design upgrades and new applications where speed and accuracy are important. all input-to- output delays have been minimized, and the current sense output is slew-rate limited to reduce noise sensitivity. fast 1.5-a peak output stages have been added to allow rapid switching of power fets. 8.2 functional block diagram 8.3 feature description uc1856 is a current mode controller, used to support various topologies such as forward, flyback, half-bridge, full bridge, push-pull configurations. current mode control is a two-loop system. the switching power supply inductor is hidden within the inner current control loop. this simplifies the design of the outer voltage control loop and improves power supply performance in many ways, including better dynamics. the objective of this inner loop is to control the state- space averaged inductor current, but in practice the instantaneous peak inductor current is the basis for control (switch current - equal to inductor current during the on time - is often sensed). if the inductor ripple current is small, peak inductor current control is nearly equivalent to average inductor current control. the peak method of inductor current control functions by comparing the upslope of inductor current (or switch current) to a current program level set by the outer loop. the comparator turns the power switch off when the instantaneous current reaches the desired level. the current ramp is usually quite small compared to the programming level, especially when v in is low. as a result, this method is extremely susceptible to noise. a noise spike is generated each time the switch turns on. a fraction of a volt coupled into the control circuit can cause it to turn off immediately, resulting in a sub-harmonic operating mode with much greater ripple. circuit layout and bypassing are critically important to successful operation. 8 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: uc1856-sp
uc1856-sp www.ti.com slusbv6 ? april 2014 feature description (continued) the peak current mode control method is inherently unstable at duty ratios exceeding 0.5, resulting in sub- harmonic oscillation. a compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. a slope compensation must be added to the sensed current waveform or subtracted from the control voltage to ensure stability above a 50% duty cycle. a compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. the pulse width modulator (pwm) of uc1856-sp is limited to a maximum duty cycle of 50%, thus it can be used in topologies such as push-pull, half bridge, full bridge, forward, flyback configurations. limiting pwm to 50% duty cycle ensures that for isolated or transformer based topologies. the transformer is allowed to reset and prevent saturation of the transformer core. pulse-by-pulse symmetry correction (flux balancing) is inherent to current mode controllers and essential for the push-pull topology to prevent core saturation. current limit control design has numerous advantages: 1. current mode control provided peak switch current limiting ? pulse by pulse current limit. 2. control loop is simplified as one pole due to output inductor is pushed to higher frequency , thus a two pole system turns into two real poles. thus system reduces to a first order system thus simplifies the control. 3. multiple converter can be paralleled and allows equal current sharing amount the various converters. 4. inherently provides for input voltage feed-forward as any perturbation in the input voltage will be reflected in the switch or inductor current. since switch or inductor current is a direct control input, thus this perturbation is very rapidly corrected. 5. the error amplifier output (outer control loop) defines the level at which the primary current (inner loop) will regulate the pulse width, and output voltage. figure 2. push-pull converter using current mode control 8.3.1 reference as highlighted in the functional block diagram , uc1856-sp incorporates a 5.1-v internal reference regulator with 10% set point variation over temperature. 8.3.2 oscillator figure 7 highlights the oscillator circuit. connecting a resistor rt from pin 9 to ground establishes a current, which is mirrored to pin 8 and charges the capacitor connected from pin 8 to ground. maximum on-time corresponds to the maximum charging time of the timing capacitor. oscillator frequency can be determined by equation 5 . off-time corresponds to capacitor discharge time establishes the converter dead time between the pulses according to equation 4 . internal 8-ma current sink discharges the ct pin capacitor. copyright ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: uc1856-sp ip d2 l1 v o d1 current mode control pwm i sense 8 v sense C v in q 1 q 2 np np r s + n s n s i s c1 C +
uc1856-sp slusbv6 ? april 2014 www.ti.com feature description (continued) 8.3.3 slope compensation for duty cycle above 50% slope compensating can be implemented by using a buffer (i.e. 2n2222) and connecting base to timing capacitor pin 8 , collector to vref (5 v), a resistor in series with emitter connected to (pin 4) cs+ of differential current sense amplifier. injecting a downslope proportional to the sawtooth into current sense amplifier. as with any bipolar pwm ic, outputs should be protected from negatively biasing the substrate. this is typically done by using schottky diodes from ground to each output. failure to do this could cause spurious interruption and restart of the oscillator, dropping of output pulses and a significant increase in propagation delays. 8.3.4 error amplifier uc1856-sp incorporates an error amplifier with typical open loop gain of 100 db and gain bandwidth of 1.5 mhz. with source and sink capability of 10 ma and 0.5 ma respectively. error amplifier sources up to 0.5 ma. figure 3. error amplifier output configuration 8.3.5 current sense amplifier uc1856-sp incorporates a differential current sense amplifier which can eliminate ground loop problems and increase noise immunity. an r-c snubber can also be implemented thus helping in blanking the peak current spike when the switch is turned on. the input of the current sense amplifier is slew rate limited allowing lower values of filter capacitors to be used to eliminate leading edge noise. figure 4. current-sense amplifier connections in some applications, a small rc filter is required to reduce switch transients. differential input allows remote noise sensing. 8.3.6 current limit over current trip point is determined by equation 1 . differential current sense amplifier has a gain of three, as shown in figure 5 . 10 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: uc1856-sp
uc1856-sp www.ti.com slusbv6 ? april 2014 feature description (continued) figure 5. pulse-by-pulse current limiting referring to figure 5 , equation 1 determines the peak current, is. (1) 8.3.7 shutdown uc1856-sp incorporates a shutdown pin (pin16). shutdown threshold voltage is 1 v. exceeding the shutdown threshold voltage causes the device to shutdown. ? if current into icl_ss v ref /r1 > 3-ma scr holding current (minimum latch current), then the device latches off. power recycle is required to un-latch the device. ? if v ref /r1 < 0.8 ma, that is icl_ss < 0.8 a, then this ensures that the circuit does not latch in a shutdown state. figure 6. shutdown latch copyright ? 2014, texas instruments incorporated submit documentation feedback 11 product folder links: uc1856-sp ref s r2v 0.5 r1 r2 is 3r ? ? - ? + ? =
uc1856-sp slusbv6 ? april 2014 www.ti.com feature description (continued) referring to figure 10 , if (2) the shutdown latch commutates when iss = 0.8 ma and a restart cycle initiates. referring to figure 11 , if (3) the device latches off until power is recycled. 8.3.8 output section uc1856-sp incorporates high current dual totem pole output stage capable of sourcing/sinking 1.5 a peak current for fast switching of power mosfets and limited to 0.5 a dc current. 8.3.9 undervoltage lockout minimum input voltage for converter is 8 v or higher, with typical value being 7.7 v. at input voltages below the actual uvlo voltage, the devices will not operate. 8.3.10 soft-start connecting a capacitor from cl/ss pin 1 to ground which is charged by 0.5-ma internal current source will determine the soft-start time. if over current is also implemented as shown in figure 5 , then ss charge time will be determined by charging ss capacitor by 0.5-ma current as well as current contributed by r1 resistor in charging the ss capacitor. 8.4 device functional modes 8.4.1 operation with v in < 8 v (minimum v in ) the devices operate with input voltages above 8 v. the maximum uvlo voltage is 8 v and will operate at input voltages above 8 v. the typical uvlo voltage is 7.7 v and the devices may operate at input voltages above that point. the devices also may operate at lower input voltages, the minimum uvlo voltage is not specified. at input voltages below the actual uvlo voltage, the devices will not operate. 8.4.2 synchronization the synchronization pin (pin10) can be configured as an output for master/slave application. when the converter is configured as a master or standalone converter, sync (pin 10) is an output. as highlighted in the functional block diagram, voltage at rt (pin 9) is greater than 4.1-v internal threshold. when using the part in slave configuration, sync pin becomes an input. typical example of parallel operation with master/slave configuration is shown in figure 12 . slave unit ct (pin 8) is grounded and rt pin is connected to vref (pin 2). when using the part in slave configuration, sync pin becomes an input. typical example of parallel operation with master/slave configuration is shown in figure 12 . slave unit ct (pin 8) is grounded and rt pin is connected to vref (pin 2). under parallel configuration two or more units can be paralleled, with comp pins tied together each will share current equally. 8.4.3 parallel operation under parallel configuration two or more units can be paralleled, with comp pins tied together each will share current equally. figure 12 highlights typical parallel operation configuration. 12 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: uc1856-sp ref v 3ma r1 > ref v 0.8ma r1 <
uc1856-sp www.ti.com slusbv6 ? april 2014 9 applications and implementation 9.1 application information uc1856-sp can be used as a controller to design various topologies such as push-pull, half-bridge, full bridge, and flyback. the following sections highlight the topologies for oscillators, error amplifiers, and parallel configurations (paralleling two evms). 9.2 typical applications 9.2.1 oscillator circuit figure 7. oscillator circuit referring to figure 7 , the size of the external capacitor, c t , determines output dead time, according to equation 4 . (4) for large values of r t : td = 250 c t . oscillator frequency is approximated by equation 5 . (5) 9.2.1.1 design requirements table 1. design parameters design parameter example value reference oscillator frequency = 200 khz r t = 10 k , c t = 1 nf equation 4 , figure 7 dead time, td = 75.8 ns r t = 10 k c t = 1 nf equation 5 , figure 7 copyright ? 2014, texas instruments incorporated submit documentation feedback 13 product folder links: uc1856-sp t t t 2 f r c = t t 2c td 3.6 8ma r = - 3 v 1.1 v
uc1856-sp slusbv6 ? april 2014 www.ti.com 9.2.1.2 detailed design procedure 9.2.1.2.1 input capacitor selection load current, duty cycle, and switching frequency are several factors which determine the magnitude of the input ripple voltage. without the input capacitor, the pulsating current of q1 would need to be completely supplied by the host source, vin, which commonly does not have sufficiently low output impedance. thus there would be substantial noise on the host dc voltage source and an increase in the conducted emi on the board. the input capacitor, cin, effectively filters the input current so the current from the host dc source is approximately an average current. the input ripple voltage amplitude is directly proportional to the output load current. the maximum input ripple amplitude occurs at maximum output load. also, the amplitude of the voltage ripple varies with the duty cycle of the converter. uc1856-sp requires a high quality ceramic, type x5r or x7r, input decoupling capacitor of at least 47 f of effective capacitance on the vin input voltage pins. in some applications additional bulk capacitance may also be required for the vin input. the effective capacitance includes any dc bias effects. the voltage rating of the input capacitor must be greater than the maximum input voltage. the capacitor must also have a ripple current rating greater than the maximum input current ripple of the uc1856-sp. the input ripple current can be calculated using equation 6 . (6) the value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. the capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. x5r and x7r ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. the output capacitor must also be selected with the dc bias taken into account. the capacitance value of a capacitor decreases as the dc bias across a capacitor increases. the input capacitance value determines the input ripple voltage of the regulator. the input voltage ripple can be calculated using equation 7 . (7) 9.2.1.2.2 output capacitor selection the output capacitance of a switching regulator is a vital part of the overall feedback system. the energy storage inductor and the output capacitor form a second-order low-pass filter. in switching power supply power stages, the function of output capacitance is to store energy. the energy is stored in the capacitor ? s electric field due to the voltage applied. thus, qualitatively, the function of a capacitor is to attempt to maintain a constant voltage. the value of output capacitance of a buck power stage is generally selected to limit output voltage ripple to the level required by the specification. since the ripple current in the output inductor is usually already determined, the series impedance of the capacitor primarily determines the output voltage ripple. the three elements of the capacitor that contribute to its impedance (and output voltage ripple) are equivalent series resistance (esr), equivalent series inductance (esl), and capacitance (c). the following gives guidelines for output capacitor selection. for continuous inductor current mode operation, to determine the amount of capacitance needed as a function of inductor current ripple, i l , switching frequency, f s , and desired output voltage ripple, v o , equation 8 is used assuming all the output voltage ripple is due to the capacitor ? s capacitance. (8) where i l is the inductor ripple current. 14 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: uc1856-sp sw iout max 0.25 vin cin f d = vout (vinmin vout) icirms iout vinmin vinmin - = l s o i c 8 f v d 3 d
uc1856-sp www.ti.com slusbv6 ? april 2014 each capacitor type is characterized by its impedance and the frequency range over which it is most effective. the frequency at which the impedance reaches its minimum is determined by its esr and esl. it is known as the self resonant frequency of the capacitor. the self resonant frequency is considered to be the maximum usable frequency for a capacitor. above this frequency the impedance of the capacitor begins to rise as the esl of the capacitor begins to dominate. note that each capacitor type has a specific frequency band over which it is most effective. therefore, a capacitor network of multiple capacitor types is more effective in reducing impedance than just one type. the current slew rate of a regulator is limited by its output filter inductor. when the amount of current required by the load changes, the initial current deficit must be supplied by the output capacitors until the regulator can meet the load demand. the desired response to a large change in the load current is the first criteria. the output capacitor needs to supply the load with current when the regulator control loop can not supply the current. this happens when load (ie: memory, processor) has a large and fast increase in current, such as a transition from no load to full load. the regulator typically needs two or more clock cycles for the control loop to see the change in load current, output voltage and adjust the duty cycle to react to the change. the output capacitor must be properly sized to supply the extra current to the load until the control loop responds to the load change. the output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. equation 9 shows the minimum output capacitance necessary to accomplish this. (9) where iout is the change in output current, f sw is the regulators switching frequency and vout is the allowable change in the output voltage. for this example, the transient load response is specified as a 5% change in vout for a load step of 1a. for this example, iout = 1.0 a and vout = 0.05 x 3.3 = 0.165 v. using these numbers gives a minimum capacitance of 25 f. this value does not take the esr of the output capacitor into account in the output voltage change. for ceramic capacitors, the esr is usually small enough to ignore in this calculation. 9.2.1.2.3 output inductor selection to calculate the value of the output inductor, use equation 10 . kind is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. the inductor ripple current is filtered by the output capacitor. therefore, choosing high inductor ripple currents impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. in general, the inductor ripple value is at the discretion of the designer; however, kind is normally from 0.1 to 0.3 for the majority of applications. vinlc refers to the voltage at the input of output lc filter. (10) the current flowing through the inductor is the inductor ripple current plus the output current. during power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. in transient conditions, the inductor current can increase up to the switch current limit of the device. for this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. 9.2.1.2.4 switching frequency initial accuracy of uc1856-sp oscillator frequency is 200 khz 15% over the temperature range. switching frequency selection is a trade-off between the overall design size and efficiency. operating at lower switching frequency will result in higher efficiency at the expense of larger solution footprint. oscillator frequency can be determined as follows: r t = 10 k (11) c t = 1 nf (12) (13) f t = 200 khz (14) copyright ? 2014, texas instruments incorporated submit documentation feedback 15 product folder links: uc1856-sp t t t 2 f r c = o sw vinlc vout vout l1 i kind vinlc f - = out o sw out 2 i c f v > d d
uc1856-sp slusbv6 ? april 2014 www.ti.com 9.2.1.3 application curves v in = 20 v t j = 25 c v in = 20 v t j = 25 c figure 8. error amplifier gain and phase vs frequency figure 9. error amplifier open-loop d.c. gain vs load resistance figure 11. shutdown without auto-restart (latched) figure 10. shutdown with auto-restart 16 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: uc1856-sp open-loop voltage gain (db) output load resistance r (k- ) l w 0 70 80 90 100 110 10 20 30 40 50 60 70 80 90 100 open-loop voltage gain (db) frequency (hz) 100 0 20 40 60 80 open-loop phase -180 o 1k 10k 100k 1m 0 o -90 o
uc1856-sp www.ti.com slusbv6 ? april 2014 9.2.2 parallel operation slaving allows parallel operation of two or more units with equal current sharing. figure 12. parallel operation 9.2.2.1 design requirements refer to design requirements for the oscillator circuit design requirements. 9.2.2.2 detailed design procedure refer to detailed design procedure for the oscillator circuit detailed design procedure. 10 power supply recommendations the devices are designed to operate from an input voltage supply range between 8 v and 40 v. this input supply should be well regulated. if the input supply is located more than a few inches from the uc1856-sp converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. a tantalum capacitor with a value of 47 f is a typical choice, however this may vary depending upon the output power being delivered. 11 layout 11.1 layout guidelines always try to use a low emi inductor with a ferrite type closed core. some examples would be toroid and encased e core inductors. open core can be used if they have low emi characteristics and are located a bit more away from the low power traces and components. make the poles perpendicular to the pcb as well if using an open core. stick cores usually emit the most unwanted noise. 11.1.1 feedback traces try to run the feedback trace as far from the inductor and noisy power traces as possible. you would also like the feedback trace to be as direct as possible and somewhat thick. these two sometimes involve a trade-off, but keeping it away from inductor emi and other noise sources is the more critical of the two. run the feedback trace on the side of the pcb opposite of the inductor with a ground plane separating the two. copyright ? 2014, texas instruments incorporated submit documentation feedback 17 product folder links: uc1856-sp
uc1856-sp slusbv6 ? april 2014 www.ti.com layout guidelines (continued) 11.1.2 input/output capacitors when using a low value ceramic input filter capacitor, it should be located as close to the vin pin of the ic as possible. this will eliminate as much trace inductance effects as possible and give the internal ic rail a cleaner voltage supply. some designs require the use of a feed-forward capacitor connected from the output to the feedback pin as well, usually for stability reasons. in this case it should also be positioned as close to the ic as possible. using surface mount capacitors also reduces lead length and lessens the chance of noise coupling into the effective antenna created by through-hole components. 11.1.3 compensation components external compensation components for stability should also be placed close to the ic. surface mount components are recommended here as well for the same reasons discussed for the filter capacitors. these should not be located very close to the inductor either. 11.1.4 traces and ground planes make all of the power (high current) traces as short, direct, and thick as possible. it is good practice on a standard pcb board to make the traces an absolute minimum of 15 mils (0.381 mm) per ampere. the inductor, output capacitors, and output diode should be as close to each other possible. this helps reduce the emi radiated by the power traces due to the high switching currents through them. this will also reduce lead inductance and resistance as well, which in turn reduces noise spikes, ringing, and resistive losses that produce voltage errors. the grounds of the ic, input capacitors, output capacitors, and output diode (if applicable) should be connected close together directly to a ground plane. it would also be a good idea to have a ground plane on both sides of the pcb. this will reduce noise as well by reducing ground loop errors as well as by absorbing more of the emi radiated by the inductor. for multi-layer boards with more than two layers, a ground plane can be used to separate the power plane (where the power traces and components are) and the signal plane (where the feedback and compensation and components are) for improved performance. on multi-layer boards the use of vias will be required to connect traces and different planes. it is good practice to use one standard via per 200 ma of current if the trace will need to conduct a significant amount of current from one plane to the other. arrange the components so that the switching current loops curl in the same direction. due to the way switching regulators operate, there are two power states. one state when the switch is on and one when the switch is off. during each state there will be a current loop made by the power components that are currently conducting. place the power components so that during each of the two states the current loop is conducting in the same direction. this prevents magnetic field reversal caused by the traces between the two half-cycles and reduces radiated emi. 18 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: uc1856-sp
uc1856-sp www.ti.com slusbv6 ? april 2014 12 device and documentation support 12.1 trademarks all trademarks are the property of their respective owners. 12.2 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.3 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2014, texas instruments incorporated submit documentation feedback 19 product folder links: uc1856-sp
package option addendum www.ti.com 30-apr-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 5962-9453001vea active cdip j 16 1 tbd a42 n / a for pkg type -55 to 125 5962-9453001ve a uc1856j-sp 5962-9453001VXC active cfp hkt 16 1 tbd call ti n / a for pkg type -55 to 125 5962-9453001vx c uc1856hkt-sp (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 30-apr-2014 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of uc1856-sp : ? catalog: uc1856 note: qualified version definitions: ? catalog - ti's standard catalog product

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